H8SSLASH2218 datasheet(163/750 Pages) RENESAS

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Section 6 Bus Controller

Rev.6.00 Jun. 03, 2008 Page 115 of 698

REJ09B0074-0600

Section 6 Bus Controller

This LSI has a built-in bus controller (BSC) that manages the external address space divided into

eight areas. The bus controller also has a bus arbitration function, and controls the operation of the

internal bus masters: the CPU and DMA controller (DMAC).

6.1

Features

• Manages external address space in area units

⎯ Manages the external space as 8 areas of 2-Mbytes

⎯ Bus specifications can be set independently for each area

⎯ Burst ROM interface can be set

• Basic bus interface*1

⎯ Chip select (CS0 to CS5) can be output for areas 0 to 5*2

⎯ 8-bit access or 16-bit access can be selected for each area

⎯ 2-state access or 3-state access can be selected for each area

⎯ Program wait states can be inserted for each area

• Burst ROM interface*2

⎯ Burst ROM interface can be selected for area 0

⎯ One or two states can be selected for the burst cycle

• Idle cycle insertion*2

⎯ Idle cycle can be inserted between consecutive read accesses to different areas

⎯ Idle cycle can be inserted before a write access to an external area immediately after a read

access to an external area

• Bus arbitration

⎯ The on-chip bus arbiter arbitrates bus mastership among CPU and DMAC

• Other features

⎯ External bus release function*2

Notes: 1. Chip select

CS6 in area 6 is for the on-chip USB. Therefore it cannot be used as an

external area. 8-bit bus mode, 3-state access, and no program wait state should be set

for area 6. Access to the RTC related registers (address: H'FFFF40 to H'FFFF5F)

follows the specification of area 7. 8-bit access, 3-state access, and no program wait

state should be set for area 7.

2. These functions are not available in the H8S/2212 Group.

BSCS207A_010020020100

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