H8SSLASH2218 datasheet(299/750 Pages) RENESAS

299 / 750 page

Section 8 I/O Ports

Rev.6.00 Jun. 03, 2008 Page 251 of 698

REJ09B0074-0600

8.9.2

Port D Data Register (PDDR)

PDDR stores output data for the port D pins.

Bit

Bit Name Initial Value

R/W

Description

PD7DR

PD6DR

PD5DR

PD4DR

PD3DR

PD2DR

PD1DR

PD0DR

R/W

Store output data for a pin that functions as a general

output port.

8.9.3

Port D Register (PORTD)

PORTD indicates the pin states of the port D.

Bit

Bit Name Initial Value

R/W

Description

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

⎯*

If the port D is read while PDDDR bits are set to 1, the

PDDR value is read. If the port D is read while PDDDR

bits are cleared to 0, the pin states are read.

Note:

After accessing EXMDLSTP or the RTC register

(address range: H'FFFF40 to H'FFFF5F), you

must perform a dummy read to the external

address space (such as H'FFEF00 to H'FF7FF)

outside the range H'FFFF40 to H'FFFF5F before

reading PORTD.

Note: * Determined by the states of pins PD7 to PD0.

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