H8SSLASH2218 datasheet(310/750 Pages) RENESAS

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Section 8 I/O Ports

Rev.6.00 Jun. 03, 2008 Page 262 of 698

REJ09B0074-0600

8.11.1

Port F Data Direction Register (PFDDR)

PFDDR specifies input or output for the pins of the port F.

Since PFDDR is a write-only register, the bit manipulation instructions must not be used to write

PFDDR. For details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.

Bit

Bit Name

Initial Value

R/W

Description

PF7DDR

PF6DDR*

PF5DDR*

PF4DDR*

PF3DDR

PF2DDR*

PF1DDR*

PF0DDR

1/0*

(H8S/2218 Group)

Modes 4 to 6:

Pin PF7 functions as the

φ output pin when the PF7DDR

bit is set to 1, and as an input port when the bit is cleared

to 0. Pins PF6 to PF3 are automatically designated as bus

control output pins. Pins PF2 to PF0 are made bus control

input/output pins by bus controller settings. Otherwise,

setting a PFDDR bit to 1 makes the corresponding pin an

output port, while clearing the bit to 0 makes the pin an

input port.

Mode 7

Setting a PFDDR bit to 1 makes the corresponding port F

pin PF6 to PF0 an output port, or in the case of pin PF7,

the

φ output pin. Clearing the bit to 0 makes the pin an

input port.

(H8S/2212 Group)

Setting a PFDDR bit to 1 makes the corresponding port F

pin PF6 to PF0 an output port, or in the case of pin PF7,

the

φ output pin. Clearing the bit to 0 makes the pin an

input port.

Notes: 1. The initial value becomes 1 in modes 4 to 6 and 0 in mode 7.

2. Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read.

This bit cannot be modified.

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