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Table 4.2

Vectored Exception Events (cont)

Exception

Type

Current

Instruction Exception Event

Priority*1

Exception

Order

Vector

Address

Vector

Offset

General

interrupt

Completed

Nonmaskable

interrupt

—

H'00000600

requests

External hardware

interrupt

4*3

—

H'00000600

Peripheral module

interrupt

4*3

—

H'00000600

Notes: 1. Priorities are indicated from high to low, 1 being highest and 4 being lowest.

2. The user defines the break point traps. 1 is a break point before instruction execution

and 11 is a break point after instruction execution. For an operand break point, use 11.

3. Use software to specify relative priorities of external hardware interrupts and peripheral

module interrupts (see section 6, Interrupt Controller (INTC)).

4.2.3

Acceptance of Exceptions

Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All

exception events are prioritized to establish an acceptance order whenever two or more exception

events occur simultaneously. The power-on reset and manual reset may not occur simultaneously,

so they have the same priority.

All general exception events occur in a relative order in the execution sequence of an instruction

(i.e., execution order), but are handled at priority level 2 in instruction-stream order (i.e., program

order), where an exception detected in a preceding instruction is accepted prior to an exception

detected in a subsequent instruction.

Three general exception events (reserved instruction code exception, unconditional trap, and

illegal slot instruction exception) are detected in the decode stage of different instructions and are

mutually exclusive events in the instruction pipeline. They have the same execution priority.

Figure 4.2 shows the order of general exception acceptance.

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