SH7708 datasheet(105/633 Pages) RENESAS

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Table 4.3

Exception Codes (cont)

Exception Type

Exception Event

Exception Code

General interrupt requests

External hardware interrupts (cont):

(cont)

IRL3–IRL0 = 1001

H'320

IRL3–IRL0 = 1010

H'340

IRL3–IRL0 = 1011

H'360

IRL3–IRL0 = 1100

H'380

IRL3–IRL0 = 1101

H'3A0

IRL3–IRL0 = 1110

H'3C0

Peripheral module interrupt:

TMU0

TUNI0

H'400

TMU1

TUNI1

H'420

TMU2

TUNI2

H'440

TICPI2

H'460

RTC

ATI

H'480

PRI

H'4A0

CUI

H'4C0

SCI

ERI

H'4E0

RXI

H'500

TXI

H'520

TEI

H'540

WDT

ITI

H'560

REF

RCMI

H'580

ROVI

H'5A0

Note:

Exception codes H'120, H'140, and H'3E0 are reserved.

4.2.5

Exception Request Masks

When the BL bit in SR is cleared to 0, exceptions and interrupts are accepted.

If a general exception event occurs when the BL bit in SR is 1, the CPU’s internal registers are set

to their post-reset state, other module registers retain their contents prior to the general exception,

and a branch is made to the same address (H'A0000000) as for a reset.

If a general interrupt occurs when BL = 1, the request is masked (held pending) and not accepted

until the BL bit is cleared to 0 by software. For reentrant exception handling, the SPC and SSR

must be saved and the BL bit in SR cleared to 0.

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