SH7708 datasheet(113/633 Pages) RENESAS

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4.6

Cautions

• Return from exception handling

 Check the BL bit in SR with software. When the SPC and SSR have been saved to external

memory, set the BL bit in SR to 1 before restoring them.

 Issue an RTE instruction. Set the SPC in the PC and SSR in SR with the RTE instruction,

branch to the SPC address, and return from exception handling.

• Operation when exception or interrupt occurs while SR.BL = 1

 Interrupt: Acceptance is suppressed until the BL bit in SR is set to 0 by software. If there is

a request and the reception conditions are satisfied, the interrupt is accepted after the

execution of the instruction that sets the BL bit in SR to 0. During the sleep or standby

mode, however, the interrupt will be accepted even when the BL bit in SR is 1.

 Exception: No user break point trap will occur even when the break conditions are met.

When one of the other exceptions occurs, a branch is made to the fixed address of the reset

(H'A0000000). In this case, the values of the EXPEVT, SPC, and SSR registers are

undefined.

• SPC when an Exception Occurs: The PC saved to the SPC when an exception occurs is as

shown below:

 Re-executing-type exceptions: The PC of the instruction that caused the exception is set in

the SPC and re-executed after return from exception handling. If the exception occurred in

a delay slot, however, the PC of the immediately prior delayed branch instruction is set in

the SPC. If the condition of the conditional delayed branch instruction is not satisfied, the

delay slot PC is set in SPC.

 Completed-type exceptions and interrupts: The PC of the instruction after the one that

caused the exception is set in the SPC. If the exception was caused by a delayed

conditional instruction, however, the branch destination PC is set in SPC. If the condition

of the conditional delayed branch instruction is not satisfied, the delay slot PC is set in

SPC.

• Initial register values after reset

 Undefined registers

R0_BANK0/1–R7_BANK0/1, R8–R15, GBR, SPC, SSR, MACH, MACL, PR

 Initialized registers

VBR = H'00000000

SR.MD = 1, SR.BL = 1, SR.RB = 1, SR.I3–SR.I0 = H'F. Other SR bits are undefined.

PC = H'A0000000

• Ensure that an exception is not generated at an RTE instruction delay slot, as operation is not

guaranteed in this case.

• When the BL bit in SR is 1, ensure that a TLB-related exception or address error is not caused

by an LDC instruction that updates SR and the following instruction, as these may be

identified as multiple exceptions and may start reset processing.

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