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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SH7708 数据表(PDF) 115 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 115 Page - Renesas Technology Corp |
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115 / 633 page  97 Section 5 Cache 5.1 Overview 5.1.1 Features The cache specifications are listed in table 5.1. Table 5.1 Cache Specifications Parameter Specification Capacity Selectable: Normal mode: 8 kbytes RAM mode: 4 kbytes cache and 4 kbytes RAM Structure Instruction/data mixed, 4-way set associative (2-way set associative in RAM mode) Line size 16 bytes Number of entries 128 entries/way Write system P0, P1, P3, U0: Write-back/write-through selectable Replacement method Least-recently-used (LRU) algorithm 5.1.2 Cache Structure The cache mixes data and instructions and uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. Each of the address and data sections is divided into 128 entries. The data section of the entry is called a line. Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 2 kbytes (16 bytes × 128 entries), with a total of 8 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache structure. |
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