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SH7708 数据表(PDF) 172 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 172 Page - Renesas Technology Corp |
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172 / 633 page  154 8.7.2 Canceling Hardware Standby Mode Hardware standby mode can only be canceled by a power-on reset. When the CA pin is driven high while the RESET pin is low and the BREQ pin is high, clock oscillation is started. Hold the RESET pin low until clock oscillation stabilizes. When the RESET pin is driven high, the CPU begins power-on reset processing. Hardware standby mode cannot be canceled by an interrupt or manual reset. 8.7.3 Hardware Standby Mode Timing Figures 8.10 and 8.11 show examples of pin timing in hardware standby mode. The CA pin is sampled using EXTAL2 (32.768 kHz), and a hardware standby request is only recognized when the pin is low for two consecutive clock cycles. The CA pin must be held low while the chip is in hardware standby mode. Clock oscillation starts when the CA pin is driven high after the RESET pin is driven low. CKIO CA RESET STATUS Normal Standby Reset 0 to 10 Bcyc Undefined Rcyc: EXTAL2 (32.768 kHz) cycle 2 Rcyc or more Figure 8.10 Hardware Standby Mode Timing (When CA Goes Low in Normal Operation) |
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