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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SH7708 数据表(PDF) 176 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 176 Page - Renesas Technology Corp |
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176 / 633 page  158 9.2 Overview of the CPG 9.2.1 CPG Block Diagram A block diagram of the on-chip clock pulse generator is shown in figure 9.1(SH7708, SH7708S) and figure 9.2(SH7708R). CAP1 CKIO Cycle = Bcyc CAP2 XTAL EXTAL MD2 MD1 MD0 FRQCR Internal bus Bus interface STBCR PLL circuit 1 ( × 1, 2, 4) Divider 1 Internal clock (I φ) Cycle = Icyc Peripheral clock (P φ) Cycle = Pcyc Standby control Divider 2 Clock pulse generator PLL circuit 2 ( × 1, 4) Crystal oscillator CPG control unit Clock frequency control circuit Standby control circuit × 1 × 1/2 × 1/4 × 1 × 1/2 × 1/4 FRQCR: Frequency control register STBCR: Standby control register Figure 9.1 Block Diagram of Clock Pulse Generator(SH7708, SH7708S) |
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