SH7708 datasheet(177/633 Pages) RENESAS

177 / 633 page

159

CAP1

CKIO

Cycle = Bcyc

CAP2

XTAL

EXTAL

MD2

MD1

MD0

FRQCR

Internal bus

Bus interface

STBCR

PLL circuit 1

(

× 1, 2, 3,4)

Divider 1

Internal

clock (I

φ)

Cycle = Icyc

Peripheral

clock (P

φ)

Cycle = Pcyc

Standby

control

Divider 2

Clock pulse generator

PLL circuit 2

(

× 1, 4)

Crystal

oscillator

CPG control unit

Clock frequency

control circuit

Standby control

circuit

× 1

× 1/2

× 1/3

× 1/4

× 1

× 1/2

× 1/3

× 1/4

FRQCR: Frequency control register

Figure 9.2 Block Diagram of Clock Pulse Generator(SH7708R)

The clock pulse generator blocks function as follows:

1. PLL Circuit 1: PLL circuit 1 doubles, triples*, quadruples, or leaves unchanged the input clock

frequency from the CKIO terminal. The multiplication rate is set by the frequency control

that it will agree with the phase of the leading edge of the CKIO pin.

2. PLL Circuit 2: PLL circuit 2 leaves unchanged or quadruples the frequency of the crystal

oscillator or the input clock frequency coming from the EXTAL pin. The multiplication ratio is

fixed by the clock operation mode. The clock operation mode is set by pins MD0, MD1, and

MD2. See table 9.3 for more information on clock operation modes.

SH7708 数据表(PDF) 177 Page - Renesas Technology Corp

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