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10.3

BSC Operation

10.3.1

Endian/Access Size and Data Alignment

The SH7708 Seires supports both big-endian mode, in which the 0 address is the most significant

byte in the byte data, and little-endian mode, in which the 0 address is the least significant byte.

Switching between the two is designated by an external pin (MD5 pin) at the time of a power-on

reset. After a power-on reset, big-endian mode is set when MD5 is low, and little-endian mode is

set when MD5 is high.

Three data bus widths are available for normal memory (byte, word, longword) and two data bus

widths (word and longword) for DRAM and pseudo-SRAM. Only longword is available for

synchronous DRAM. For the PCMCIA interface, choose from byte and word. This means data

alignment is done by matching the device’s data width and endian. The access unit must also be

matched to the device’s bus width. This also means that when longword data is read from a byte-

width device, four read operations must be executed. In the SH7708 Series, data alignment and

conversion of data length is performed automatically between the respective interfaces.

Tables 10.6 through 10.11 show the relationship between endian, device data width, and access

unit.

Table 10.6

32-Bit External Device/Big Endian Access and Data Alignment

Data Bus

Strobe Signal

Operation

D31–D24 D23–D16 D15–D8 D7–D0

WE3,

CASHH,

DQMUU

WE2,

CASHL,

DQMUL

WE1,

CASLH,

DQMLU

WE0,

CASLL,

DQMLL

Address 0

byte access

Data

7–0

—

Asserted —

—

Address 1

byte access

—

Data

7–0

—

Asserted —

—

Address 2

byte access

—

Data

7–0

—

Asserted —

Address 3

byte access

—

Data

7–0

—

Asserted

Address 0

word access

Data

15–8

Data

7–0

—

Asserted Asserted —

—

Address 2

word access

—

Data

15–8

Data

7–0

—

Asserted Asserted

Address 0

longword

access

Data

31–24

Data

23–16

Data

15–8

Data

7–0

Asserted Asserted Asserted Asserted

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