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Bit 2—Refresh Count Overflow Flag (OVF): Status flag that indicates when the number of refresh

requests indicated in the refresh count register (RFCR) exceeds the limit set in the LMTS bit in

RTCSR.

Bit 2: OVF

Description

RFCR has not exceeded the count limit value set in LMTS

Clearing Condition: When 0 is written to OVF

(Initial value)

RFCR has exceeded the count limit value set in LMTS

Setting Condition: When the RFCR value has exceeded the count limit value

set in LMTS*

Note:

Contents do not change when 1 is written to OVF.

Bit 1—Refresh Count Overflow Interrupt Enable (OVIE): Selects whether to suppress generation

of interrupt requests by OVF when the OVF bit of RTCSR is set to 1.

Bit 1: OVIE

Description

Disables interrupt requests caused by OVF

(Initial value)

Enables interrupt requests caused by OVF

Bit 0—Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be

compared to the number of refreshes indicated in the refresh count register (RFCR). When the

value RFCR exceeds the value specified by LMTS, the OVF flag is set.

Bit 0: LMTS

Description

Count limit value is 1024

(Initial value)

Count limit value is 512

10.2.10

Refresh Timer Counter (RTCNT)

RTCNT is a 16-bit read/write register containing an 8-bit counter that counts up on an input clock.

The clock select bits (CKS2–CKS0) in RTCSR select the input clock. When RTCNT matches

RTCOR, the OVF bit in RTCSR is set and RTCNT is cleared. RTCNT is initialized to H'00 by a

power-on reset; it continues incrementing after a manual reset; it is not initialized in standby

mode, but retains its contents.

Note:

The method for writing to RTCOR is different from that for general registers to prevent

inadvertent overwriting. Using a word transfer instruction, place B'10100101 in the upper

byte and the write data in the lower byte. For details, see section 10.2.13, Cautions on

Accessing Refresh Control Related Registers.

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