SH7708 datasheet(236/633 Pages) RENESAS

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H'FFFD000 (address Y) + H'08C0 (value X), or H'FFFFD8C0. As a result, H'0230 is written to

the SDMR register. When H'0230 is written to the SDMR register of area 3, random data is

written to the address H'FFFE000 (address Y) + H'08C0 (value X) or H'FFFFE8C0. As a result,

H'0230 is written to the SDMR register. The range for value X is H'000 to H'0FFC.

Address bits

Bit:

Bit name:

SDMR address

Initial value:

—

· · · · · · · · · · · · ·

—

R/W:

—

· · · · · · · · · · · · ·

—

Bit:

Bit name:

Initial value:

—

R/W:

—

Note:

Depending on the type of synchronous DRAM.

10.2.9

Refresh Timer Control/Status Register (RTCSR)

The refresh timer control/status register (RTSCR) is a 16-bit read/write register that specifies the

refresh cycle, whether to generate an interrupt, and the cycle of that interrupt. RTSCR is initialized

to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.

Note:

The method for writing to RTCOR is different from that for general registers to prevent

inadvertent overwriting. Using a word transfer instruction, place B'10100101 in the upper

byte and the write data in the lower byte. For details, see section 10.2.13, Cautions on

Accessing Refresh Control Related Registers.

Bit:

Bit name:

—

Initial value:

R/W:

Bit:

Bit name:

CMF

CMIE

CKS2

CKS1

CKS0

OVF

OVIE

LMTS

Initial value:

R/W:

R/W

Bits 15 to 8—Reserved: These bits always read 0.

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