SH7708 datasheet(271/633 Pages) RENESAS

271 / 633 page

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1. Normally, set the refresh counter count value to the optimum value for the L version (e.g. 1024

cycles/128 ms).

2. When a transition is made to self-refreshing:

a. Provide an interrupt handler to restore the refresh counter count value to the optimum value

for the L version (e.g. 1024 cycles/128 ms) when a refresh counter overflow interrupt is

generated.

b. Reset the refresh counter count value to the requested short cycle (e.g. 1024 cycles/16 ms),

set refresh controller overflow interruption, and clear the refresh count register (RFCR) to

c. Set self-refresh mode.

This procedure causes refreshing immediately following a self-refresh to occur in a short cycle.

When adequate refreshing ends, an interrupt is generated and the setting can be restored to the

original refresh cycle.

CAS-before-RAS refreshing is performed in normal operation, in sleep mode, and in a manual

reset.

Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in a manual

reset.

When the bus has been released in response to a bus arbitration request, or when a transition is

made to standby mode, signals generally become high-impedance. Controlling the

RAS and CAS

signals to become high-impedance or continue to be output is performed with the HIZCNT bit in

BCR1. This enables the DRAM to be kept in the self-refreshing state.

SH7708 数据表(PDF) 271 Page - Renesas Technology Corp