SH7708 datasheet(273/633 Pages) RENESAS

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10.3.5

Synchronous DRAM Interface

Synchronous DRAM Direct Connection: Since synchronous DRAM can be selected by the

signal, physical space areas 2 and 3 can be connected using

RAS and other control signals in

common. If the memory type bits (DRAMTP2–DRAMTP0) in BCR1 are set to 010, area 2 is

normal memory space and area 3 is synchronous DRAM space; if set to 011, areas 2 and 3 are

both synchronous DRAM space.

With the SH7708 Series, burst length 1 burst read/single write mode is supported as the

synchronous DRAM operating mode. The data bus width is fixed at 32 bits, and the size bit (SZ)

in MCR must be set to 1. The burst enable bit (BE) in MCR is ignored, a16-bit burst transfer is

performed in a cache fill/copy-back cycle, and only one access is performed in a write-through

area write or a noncacheable area read/write.

The control signals for direct connection of synchronous DRAM are

RAS, CAS, RD/WR, CS2 or

CS3, DQMUU, DQMUL, DQMLU, DQMLL, and CKE. All the signals other than CS2 and CS3

are common to all areas, and signals other than CKE are valid and fetched to the synchronous

DRAM only when

CS2 or CS3 is asserted. Synchronous DRAM can therefore be connected in

parallel to a number of areas. CKE is negated (low) only when self-refreshing is performed,

otherwise it is asserted (high).

Commands for synchronous DRAM are specified by

RAS, CAS, RD/WR, and special address

signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks

(PALL), precharge specified bank (P RE), row address strobe bank active (ACTV), read (READ),

read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register

write (MRS).

Byte specification is performed by DQMUU, DQMUL, DQMLU, and DQMLL. A read/write is

performed for the byte for which the corresponding DQM is low. In big-endian mode, DQMUU

specifies an access to address 4n, and DQMLL specifies an access to address 4n + 3. In little-

endian mode, DQMUU specifies an access to address 4n + 3, and DQMLL specifies an access to

address 4n.

Figure 10.23 shows an example of the connection of 256k

× 16-bit synchronous DRAMs.

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