SH7708 datasheet(276/633 Pages) RENESAS

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Table 10.14 Example of Correspondence between SH7708 Series and Synchronous DRAM

Address Pins (AMX (1-0) = 11)

SH7708 Series Address Pin

Synchronous

RAS Cycle

CAS Cycle

DRAM Address Pin

Function

A11

A19

BANK select bank address

A10

A18

L/H

Address precharge setting

A17

Address

A16

A15

A14

A13

A12

A11

A10

Not used

—

Not used

Burst Read: The timing chart for a burst read is shown in figure 10.24. In the following example

it is assumed that four 2M

× 8-bit synchronous DRAMs are connected and a 32-bit data width is

used, and the burst length is 1. Following the Tr cycle in which ACTV command output is

performed, a READ command is issued in the Tc1, Tc2, and Tc3 cycles, and a READA command

in the Tc4 cycle. The read data is then accepted on the rising edge of the external command clock

(CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is used to wait for completion of auto-

precharge based on the READA command inside the synchronous DRAM; no new access

command can be issued to the same bank during this cycle, but access to synchronous DRAM for

another area is possible. In the SH7708 Series, the number of Tpc cycles is determined by the TPC

bit specification in MCR, and commands cannot be issued for the same synchronous DRAM

during this interval.

The example in figure 10.24 shows the basic timing. To connect slower synchronous DRAM, the

cycle can be extended by setting the WCR2 and MCR bits. The number of cycles from the ACTV

command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by the

RCD bit in MCR, with a value of 0 to 3 specifying 1 to 4 cycles, respectively. For 2 or more

cycles, a Trw cycle, in which an NOP command is issued for the synchronous DRAM, is inserted

between the Tr cycle and the Tc cycle. The number of cycles from READ and READA command

output cycles Tc1–Tc4 to the first read data latch cycle, Td1, can be specified as 1 to 3 cycles

independently for areas 2 and 3 by means of A1–2W1 and A1–2W0 or A3W1 and A3W0 in

WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency

cycles.

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