SH7708 datasheet(287/633 Pages) RENESAS

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Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed

after powering on. To perform synchronous DRAM initialization correctly, the bus state controller

registers must first be set, followed by a write to the synchronous DRAM mode register. In

synchronous DRAM mode register setting, the address signal value at that time is latched by a

combination of the

RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state

controller provides for value X to be written to the synchronous DRAM mode register by

performing a write to address H'FFFFD000 + X for area 2 synchronous DRAM, and to address

H'FFFFE000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the

mode write is performed as a byte-size access. To set burst read/write, CAS latency 1 to 3, wrap

type = sequential, and burst length 1 supported by the SH7708 Series, arbitrary data is written in a

byte-size access to the following addresses:

Area 2

Area 3

CAS latency 1

CAS latency 2

CAS latency 3

FFFFD840

FFFFD880

FFFFD8C0

FFFFE840

FFFFE880

FFFFE8C0

Mode register setting timing is shown in figure 10.32.

As a result of the write to address H'FFFFD000 + X or H'FFFFE000 + X, a precharge all banks

(PALL) command is first issued in the TRp1 cycle, then a mode register write command is issued

in the TMw1 cycle.

Before mode register setting, a 100 µs idle time (depending on the memory manufacturer) must be

guaranteed after powering on requested by the synchronous DRAM. If the reset signal pulse width

is greater than this idle time, there is no problem in performing mode register setting immediately.

The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must

be executed. This is usually achieved automatically through various initialization methods after

auto-refresh setting. However, a more dependable method is to set a short refresh request

generation interval just as these dummy cycles are being executed. With simple read or write

access, the address counter in the synchronous DRAM used for auto-refreshing is not initialized,

and so the cycle must always be an auto-refresh cycle.

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