SH7708 datasheet(315/633 Pages) RENESAS

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IRQOUT Pin Assertion Conditions:

• When a memory refresh request has been generated but the refresh cycle has not yet begun

• When an interrupt is generated with an interrupt request level higher than the setting of the

interrupt mask bits (I3–I0) in the status register (SR). (This does not depend on the SR.BL bit.)

10.4

Usage Notes

10.4.1

Area 2 and 3 Bus Width Setting

Note the following concerning the SH7708 (not including the SH7708S and SH7708R).

When SDRAM, DRAM, or PSRAM is connected, cases such as the following can be envisaged in

which the contents of register BCR2, which sets the bus width of each area, and the MCR.SZ bits,

which set the bus width of SDRAM, DRAM, and PSRAM, are different.

• A setting other than 32 bits in the BCR2 register and MCR register when SDRAM is

connected

• A setting of 16 bits in the BCR2 register and 32 bits in the MCR register when DRAM is

connected in area 3 only

• A setting of 32 bits in the BCR2 register and 16 bits in the MCR register when DRAM is

connected in area 3 only

• A setting other than 16 bits in the BCR2 register and MCR register when DRAM is connected

in areas 2 and 3

• Different bus width settings in the BCR register and MCR register when PSRAM is connected

In these cases, one of the following settings should be made.

• When SDRAM is connected, use a 32-bit bus width setting in the BCR2 register and MCR

• When DRAM is connected in area 3 only, use the same bus width setting (16 or 32 bits) in the

BCR2 register and MCR register.

• When DRAM is connected in areas 2 and 3, use a 16-bit bus width setting in the BCR2 register

and MCR register.

• When PSRAM is connected, use the same bus width setting (16 or 32 bits) in the BCR2

10.4.2

When Area 6 is Designated for PCMCIA, with a 16-Bit Bus Width

Note the following concerning the SH7708 Series (SH7708, SH7708S, SH7708R).

SH7708 数据表(PDF) 315 Page - Renesas Technology Corp