H8SLASH3003 datasheet(383/715 Pages) RENESAS

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10.5.3 Interrupt Sources and DMA Controller Activation

Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input

capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all

independently vectored. An interrupt is requested when the interrupt request flag and interrupt

enable bit are both set to 1.

The priority order of the channels can be modified in interrupt priority registers A and B (IPRA

and IPRB). For details see section 5, Interrupt Controller.

Compare match/input capture A interrupts in channels 0 to 3 can activate the DMA controller

(DMAC). When the DMAC is activated a CPU interrupt is not requested.

Table 10-10 lists the interrupt sources.

Table 10-10 ITU Interrupt Sources

Interrupt

DMAC

Channel

Source

Description

Activatable

Priority*

IMIA0

Compare match/input capture A0

Yes

High

IMIB0

Compare match/input capture B0

OVI0

Overflow 0

IMIA1

Compare match/input capture A1

Yes

IMIB1

Compare match/input capture B1

OVI1

Overflow 1

IMIA2

Compare match/input capture A2

Yes

IMIB2

Compare match/input capture B2

OVI2

Overflow 2

IMIA3

Compare match/input capture A3

Yes

IMIB3

Compare match/input capture B3

OVI3

Overflow 3

IMIA4

Compare match/input capture A4

IMIB4

Compare match/input capture B4

OVI4

Overflow 4

Low

Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be changed

by settings in IPRA and IPRB.

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