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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3003 数据表(PDF) 403 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 403 Page - Renesas Technology Corp |
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403 / 715 page  11.2 Register Descriptions 11.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must be set to 1. For further information about PADDR, see section 9.8, Port A. 11.2.2 Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when these TPC output groups are used. For further information about PADR, see section 9.8, Port A. Bit Initial value Read/Write 7 PA DDR 0 W Port A data direction 7 to 0 These bits select input or output for port A pins 7 6 PA DDR 0 W 6 5 PA DDR 0 W 5 4 PA DDR 0 W 4 3 PA DDR 0 W 3 2 PA DDR 0 W 2 1 PA DDR 0 W 1 0 PA DDR 0 W 0 Bit Initial value Read/Write 0 PA 0 R/(W) 0 1 PA 0 R/(W) 1 2 PA 0 R/(W) 2 3 PA 0 R/(W) 3 4 PA 0 R/(W) 4 5 PA 0 R/(W) 5 6 PA 0 R/(W) 6 7 PA 0 R/(W) 7 Port A data 7 to 0 These bits store output data for TPC output groups 0 and 1 * * ** ** * * Note: Bits selected for TPC output by NDERA settings become read-only bits. * 385 |
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