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H8/3003 数据表(PDF) 419 Page - Renesas Technology Corp

部件名 H8/3003
功能描述  microcontroller (MCU)
PDF  715 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8/3003 数据表(HTML) 419 Page - Renesas Technology Corp

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Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11-5 shows
an example in which the TPC is used for cyclic five-phase pulse output.
Figure 11-5 Normal TPC Output Example (Five-Phase Pulse Output)
GRA
H'0000
NDRB
PBDR
TP15
TP14
TP13
TP12
TP11
•
•
•
•
Time
80
TCNT
TCNT value
C0
40
60
20
30
10
18
08
88
80
C0
Compare match
The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare
register and the counter will be cleared by compare match A. The trigger period is set in GRA.
The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt.
H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Output data H'80 is written in NDRB.
The timer counter in this ITU channel is started. When compare match A occurs, the NDRB contents
are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt service routine
writes the next output data (H'C0) in NDRB.
Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing
H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts. If the DMAC is set for
activation by this interrupt, pulse output can be obtained without loading the CPU.
00
80
C0
40
60
20
30
10
18
08
88
80
C0
40
401



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