H8SLASH3003 datasheet(435/715 Pages) RENESAS

435 / 715 page

12.3 Operation

Operations when the WDT is used as a watchdog timer and as an interval timer are described

below.

12.3.1 Watchdog Timer Operation

Figure 12-4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the

WT/

IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the

TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and

overflows due to a system crash etc., the H8/3003 is internally reset for a duration of 518 states.

The watchdog reset signal can be externally output from the

RESO pin to reset external system

devices. The reset signal is output externally for 132 states. External output can be enabled or

disabled by the RSTOE bit in RSTCSR.

A watchdog reset has the same vector as a reset generated by input at the

RES pin. Software can

distinguish a

RES reset from a watchdog reset by checking the WRST bit in RSTCSR.

If a

RES reset and a watchdog reset occur simultaneously, the RES reset takes priority.

Figure 12-4 Watchdog Timer Operation

H'FF

H'00

RESO

WDT overflow

Start

H'00 written

in TCNT

Reset

TME set to 1

H'00 written

in TCNT

Internal

reset signal

518 states

132 states

TCNT count

value

OVF = 1

417

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