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H8/3003 数据表(PDF) 439 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 439 Page - Renesas Technology Corp |
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439 / 715 page  12.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR. 12.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not incremented. See figure 12-8. Figure 12-8 Contention between TCNT Write and Increment Changing CKS2 to CKS0 Values: Halt TCNT by clearing the TME bit to 0 in TCSR before changing the values of bits CKS2 to CKS0. ø TCNT TCNT NM Counter write data T3 T2 T1 Write cycle: CPU writes to TCNT Internal write signal TCNT input clock 421 |
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