H8SLASH3003 datasheet(505/715 Pages) RENESAS

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14.2 Register Descriptions

14.2.1 A/D Data Registers A to D (ADDRA to ADDRD)

The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the

results of A/D conversion.

An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data

upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an

A/D data register are reserved bits that always read 0. Table 14-3 indicates the pairings of analog

input channels and A/D data registers.

The CPU can always read and write the A/D data registers. The upper byte can be read directly,

but the lower byte is read through a temporary register (TEMP). For details see section 14.3, CPU

Interface.

The A/D data registers are initialized to H'0000 by a reset and in standby mode.

Table 14-3 Analog Input Channels and A/D Data Registers

Analog Input Channel

Group 0

Group 1

A/D Data Register

AN0

AN4

ADDRA

AN1

AN5

ADDRB

AN2

AN6

ADDRC

AN3

AN7

ADDRD

Bit

ADDRn

Initial value

AD8

AD6

AD4

AD2

AD0

—

AD9

AD7

AD5

AD3

AD1

—

A/D conversion data

10-bit data giving an

A/D conversion result

Reserved bits

Read/Write

(n = A to D)

487

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