H8SLASH3003 datasheet(613/715 Pages) RENESAS

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DTCR0A—Data Transfer Control Register 0A

H'27

DMAC0

(cont)

•

Full address mode

Bit

Initial value

Read/Write

DTE

R/W

DTSZ

R/W

SAID

R/W

SAIDE

R/W

DTIE

R/W

DTS0A

R/W

DTS2A

R/W

DTS1A

R/W

Data transfer enable

Data transfer is disabled

Data transfer is enabled

Source address increment/decrement

Data transfer interrupt enable

Data transfer select 0A

Normal mode

Block transfer mode

Data transfer select 2A and 1A

Set both bits to 1

Data transfer size

Byte-size transfer

Word-size transfer

Increment/Decrement Enable

MARA is held fixed

Decremented:

SAID

Bit 5

SAIDE

Bit 4

Incremented:

Interrupt request by DTE bit is disabled

Interrupt request by DTE bit is enabled

If DTSZ = 0, MARA is decremented by 1 after each transfer

If DTSZ = 1, MARA is decremented by 2 after each transfer

If DTSZ = 0, MARA is incremented by 1 after each transfer

If DTSZ = 1, MARA is incremented by 2 after each transfer

595

H8/3003 数据表(PDF) 613 Page - Renesas Technology Corp

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