H8SLASH3003 datasheet(617/715 Pages) RENESAS

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DTCR0B—Data Transfer Control Register 0B

H'2F

DMAC0

•

Short address mode

Bit

Initial value

Read/Write

DTE

R/W

DTSZ

R/W

DTID

R/W

RPE

R/W

DTIE

R/W

DTS0

R/W

DTS2

R/W

DTS1

R/W

Data transfer enable

Data transfer is disabled

Data transfer is enabled

Data transfer size

Byte-size transfer

Word-size transfer

Data transfer increment/decrement

Incremented:

Decremented:

Data transfer select

DTS2

Data transfer interrupt enable

Interrupt requested by DTE bit is disabled

Interrupt requested by DTE bit is enabled

CPU interrupt requested when DTE = 0

Data Transfer Activation Source

Compare match/input capture A interrupt from ITU channel 0

Compare match/input capture A interrupt from ITU channel 1

Compare match/input capture A interrupt from ITU channel 2

Compare match/input capture A interrupt from ITU channel 3

SCI transmit-data-empty interrupt

SCI receive-data-full interrupt

Falling edge of

input

Bit 2

DTS1

Bit 1

DTS0

Bit 0

Repeat enable

Description

I/O mode

Repeat mode

Idle mode

RPE

DTIE

Low level of

input

DREQ

If DTSZ = 0, MAR is incremented by 1 after each transfer

If DTSZ = 1, MAR is incremented by 2 after each transfer

If DTSZ = 0, MAR is decremented by 1 after each transfer

If DTSZ = 1, MAR is decremented by 2 after each transfer

599

H8/3003 数据表(PDF) 617 Page - Renesas Technology Corp

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