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H8/3003 数据表(PDF) 618 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 618 Page - Renesas Technology Corp |
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618 / 715 page ![]() DTCR0B—Data Transfer Control Register 0B H'2F DMAC0 • Full address mode Bit Initial value Read/Write 7 DTME 0 R/W 6 — 0 R/W 5 DAID 0 R/W 4 DAIDE 0 R/W 3 TMS 0 R/W 0 DTS0B 0 R/W 2 DTS2B 0 R/W 1 DTS1B 0 R/W Data transfer master enable 0 Data transfer is disabled 1 Data transfer is enabled Destination address increment/decrement Increment/Decrement Enable MARB is held fixed MARB is held fixed Decremented: 0 1 0 1 0 1 DAID Bit 5 DAIDE Bit 4 Incremented: Transfer mode select 0 Destination is the block area in block transfer mode 1 Source is the block area in block transfer mode Data transfer select 2B to 0B DTS2B 0 1 Normal Mode Auto-request (burst mode) Not available Auto-request (cycle-steal mode) Not available Not available Not available Falling edge of Bit 2 DTS1B 0 1 0 1 Bit 1 DTS0B 0 1 0 1 0 1 Bit 0 0 Low level input at 1 Data Transfer Activation Source Block Transfer Mode Compare match/input capture A from ITU channel 0 Compare match/input capture A from ITU channel 1 Compare match/input capture A from ITU channel 2 Compare match/input capture A from ITU channel 3 Not available Not available Falling edge of Not available DREQ DREQ DREQ If DTSZ = 0, MARB is incremented by 1 after each transfer If DTSZ = 1, MARB is incremented by 2 after each transfer If DTSZ = 0, MARB is decremented by 1 after each transfer If DTSZ = 1, MARB is decremented by 2 after each transfer 600 |
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