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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3003 数据表(PDF) 657 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 657 Page - Renesas Technology Corp |
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657 / 715 page  TCSR—Timer Control/Status Register H'A8 WDT Bit Initial value Read/Write 7 OVF 0 R/(W) 6 WT/ 0 R/W 5 TME 0 R/W 4 — 1 — 3 — 1 — 0 CKS0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W Overflow flag Timer mode select IT 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] TCNT changes from H'FF to H'00 0 Interval timer: requests interval timer interrupts 1 Watchdog timer: generates a reset signal Clock select 2 to 0 0 1 ø/2 ø/32 ø/64 ø/128 ø/256 ø/512 ø/2048 0 1 0 1 0 1 0 1 0 1 0 ø/4096 1 Timer enable 0 Timer disabled • 1 Timer enabled TCNT is initialized to H'00 and halted • • TCNT is counting CPU interrupt requests are enabled Note: Only 0 can be written, to clear the flag. * * 639 |
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