H8SLASH3003 datasheet(659/715 Pages) RENESAS

659 / 715 page

RFSHCR—Refresh Control Register

H'AC

Refresh controller

Bit

Initial value

Read/Write

SRFMD

R/W

PSRAME

R/W

DRAME

R/W

CAS/

R/W

M9/

R/W

RCYCE

R/W

RFSHE

R/W

—

Self-refresh mode

DRAM or PSRAM self-refresh is disabled in software standby mode

DRAM or PSRAM self-refresh is enabled in software standby mode

Refresh cycle enable

Refresh pin enable

PSRAM enable, DRAM enable

Refresh cycles are disabled

Refresh cycles are enabled for area 3

Address multiplex mode select

8-bit column address mode

9-bit column address mode

Strobe mode select

mode

Can be used as an interval timer

PSRAM can be connected

Illegal setting

Bit 6

Bit 5

RAM Interface

PSRAME DRAME

DRAM can be connected

Refresh signal output at the

pin is disabled

Refresh signal output at the

pin is enabled

RFSH

CAS

641

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