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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3003 数据表(PDF) 709 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 709 Page - Renesas Technology Corp |
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709 / 715 page  Appendix D Pin States D.1 Port States in Each Mode Table D-1 Port States Hardware Software Bus- Program Pin Reset Standby Standby Released Execution Name Mode State Mode Mode Mode Sleep Mode ø — Clock output T H Clock output Clock output A19 to A0 1 to 4 L T T T A19 to A0 D15 to D8 1 to 4 T T T T D15 to D0 AS, RD, 1 to 4 H T T T AS, RD, HWR, LWR HWR, LWR P47 to P40 1 to 4 8-bit bus T T keep keep I/O port D7 to D0 16-bit bus T T D7 to D0 P57 to P54 1, 2 T T keep keep I/O port A23 to A20 3, 4 L T T T A23 to A20 P60 1 to 4 T T keep keep I/O port*1 WAIT P61 1 to 4 T T (BRLE = 0) T I/O port keep BREQ (BRLE = 1) T P62 1 to 4 T T (BRLE = 0) I/O port keep L (BRLE = 0) (BRLE = 1) or BACK H (BRLE = 1) P77 to P70 1 to 4 T T T T Input port Note: * Do not set the DDR bit to 1. Legend H: High L: Low T: High-impedance state keep: Input pins are in the high-impedance state; output pins maintain their previous state. DDR: Data direction register bit 691 |
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