H8SLASH3003 datasheet(712/715 Pages) RENESAS

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H8/3003 数据表(PDF) 712 Page - Renesas Technology Corp

部件名	H8/3003

功能描述	microcontroller (MCU)

PDF	715 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

712 / 715 page

Reset in T2 State: Figure D-2 is a timing diagram for the case in which RES goes low during the

T2 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to

the input state.

AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance

state. The address bus is initialized to the low output level 0.5 state after the low level of

RES is

sampled. The same timing applies when a reset occurs during a wait state (TW).

Figure D-2 Reset during Memory Access (Reset during T2 State)

Address bus

CS to CS

RD (read access)

HWR, LWR

Data bus

I/O port

RES

H'000000

High impedance

Internal

reset signal

Access to external address

(write access)

694

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