H8SLASH3003 datasheet(121/715 Pages) RENESAS

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6.1.3 Input/Output Pins

Table 6-1 summarizes the bus controller’s input/output pins.

Table 6-1 Bus Controller Pins

Name

Abbreviation

I/O

Function

Chip select 0 to 7

CS0 to CS7

Output

Strobe signals selecting areas 0 to 7

Address strobe

Output

Strobe signal indicating valid address output on the

address bus

Read

Output

Strobe signal indicating reading from the external

address space

High write

HWR

Output

Strobe signal indicating writing to the external

address space, with valid data on the upper data

bus (D15 to D8)

Low write

LWR

Output

Strobe signal indicating writing to the external

address space, with valid data on the lower data

bus (D7 to D0)

Wait

WAIT

Input

Wait request signal for access to external three-

state-access areas

Bus request

BREQ

Input

Request signal for releasing the bus to an external

device

Bus acknowledge

BACK

Output

Acknowledge signal indicating the bus is released

to an external device

6.1.4 Register Configuration

Table 6-2 summarizes the bus controller’s registers.

Table 6-2 Bus Controller Registers

Initial Value

Address*

Name

R/W

Modes 1 & 3 Modes 2 & 4

H'FFEC

Bus width control register

ABWCR

R/W

H'FF

H'00

H'FFED

Access state control register

ASTCR

R/W

H'FF

H'FFEE

Wait control register

WCR

R/W

H'F3

H'FFEF

Wait state controller enable register

WCER

R/W

H'FF

H'FFF3

Bus release control register

BRCR

R/W

H'FE

Note: * Lower 16 bits of the address.

Abbrevi-

ation

103

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