H8SLASH3003 datasheet(147/715 Pages) RENESAS

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6.3.7 Bus Arbiter Operation

The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are

four bus masters: the CPU, DMA controller (DMAC), refresh controller, and an external bus

master. When a bus master has the bus right it can carry out read, write, or refresh access. Each

bus master uses a bus request signal to request the bus right. At fixed times the bus arbiter

determines priority and uses a bus acknowledge signal to grant the bus to a bus master, which can

then operate using the bus.

The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and

returns an acknowledge signal to the bus master if the bus request signal is active. When two or

more bus masters request the bus, the highest-priority bus master receives an acknowledge signal.

The bus master that receives an acknowledge signal can continue to use the bus until the

acknowledge signal is deactivated.

The bus master priority order is:

(High)

External bus master > refresh controller > DMAC > CPU

(Low)

The bus arbiter samples the bus request signals and determines priority at all times, but it does not

always grant the bus immediately, even when it receives a bus request from a bus master with

higher priority than the current bus master. Each bus master has certain times at which it can

release the bus to a higher-priority bus master.

CPU: The CPU is the lowest-priority bus master. If the DMAC, refresh controller, or an external

bus master requests the bus while the CPU has the bus right, the bus arbiter transfers the bus right

to the bus master that requested it. The bus right is transferred at the following times:

•

The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two

consecutive byte accesses, however, the bus right is not transferred between the two byte

accesses.

•

If another bus master requests the bus while the CPU is performing internal operations, such

as executing a multiply or divide instruction, the bus right is transferred immediately. The

CPU continues its internal operations.

•

If another bus master requests the bus while the CPU is in sleep mode, the bus right is

transferred immediately.

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