H8SLASH3003 datasheet(148/715 Pages) RENESAS

148 / 715 page

DMAC: When the DMAC receives an activation request, it requests the bus right from the bus

arbiter. If DMAC is a bus master and the refresh controller or an external bus master requests the

bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested the

bus. The bus right is transferred at the following times.

The bus right is transferred when the DMAC finishes transferring 1 byte or 1 word. A DMAC

transfer cycle consists of a read cycle and a write cycle. The bus right is not transferred between

the read cycle and the write cycle.

There is a priority order among the DMAC channels. For details see section 8.4.9, Multiple-

Channel Operation.

Refresh Controller: When a refresh cycle is requested, the refresh controller requests the bus

right from the bus arbiter. When the refresh cycle is completed, the refresh controller releases the

bus. For details see section 7, Refresh Controller.

External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an

external bus master. The external bus master has highest priority, and requests the bus right from

the bus arbiter by driving the

BREQ signal low. Once the external bus master gets the bus, it keeps

the bus right until the

BREQ signal goes high. While the bus is released to an external bus master,

the H8/3003 holds the address bus and data bus control signals (

AS, RD, HWR, and LWR) in the

high-impedance state, and holds the

BACK pin in the low output state.

The bus arbiter samples the

BREQ pin at the rise of the system clock (ø). If BREQ is low, the bus

is released to the external bus master at the appropriate opportunity. The

BREQ signal should be

held low until the

BACK signal goes low.

When the

BREQ pin is high in two consecutive samples, the BACK signal is driven high to end

the bus-release cycle.

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H8/3003 数据表(PDF) 148 Page - Renesas Technology Corp