H8SLASH3003 datasheet(170/715 Pages) RENESAS

170 / 715 page

Operation in Power-Down State: The refresh controller operates in sleep mode. It does not

operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR,

RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby

mode.

Example 1: Connection to 2

WE 1-Mbit DRAM (1-Mbyte Mode): Figure 7-7 shows typical

interconnections to a 2

WE 1-Mbit DRAM, and the corresponding address map. Figure 7-8 shows

a setup procedure to be followed by a program for this example. After power-up the DRAM must

be refreshed to initialize its internal state. Initialization takes a certain length of time, which can be

measured by using an interrupt from another timer module, or by counting the number of times

RTMCSR bit 7 (CMF) is set. Note that no refresh cycle is executed for the first refresh request

after exit from the reset state or standby mode (the first time the CMF flag is set; see figure 7-3).

When using this example, check the DRAM device characteristics carefully and use a procedure

that fits them.

Figure 7-7 Interconnections and Address Map for 2

WE 1-Mbit DRAM (Example)

H8/3003

HWR

LWR

to D 0

RAS

CAS

I/O

to I/O

H'60000

H'7FFFF

a. Interconnections (example)

DRAM area

Area 3 (1-Mbyte mode)

b. Address map

1-Mbit DRAM with

16-bit organization

152

H8/3003 数据表(PDF) 170 Page - Renesas Technology Corp