H8SLASH3003 datasheet(209/715 Pages) RENESAS

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Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables or

disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the channel

is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the channel

waits for transfers to be requested. When the specified number of transfers have been completed,

the DTE bit is automatically cleared to 0. When DTE is 0, the channel is disabled and does not

accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1.

Bit 7

DTE

Description

Data transfer is disabled (DTE is cleared to 0 when the specified number

(Initial value)

of transfers have been completed)

Data transfer is enabled

If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.

Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.

Bit 6

DTSZ

Description

Byte-size transfer

(Initial value)

Word-size transfer

Bit 5—Source Address Increment/Decrement (SAID) and Bit 4—Source Address

Increment/Decrement Enable (SAIDE): These bits select whether the source address register

(MARA) is incremented, decremented, or held fixed during the data transfer.

Bit 5

Bit 4

SAID

SAIDE

Description

MARA is held fixed

(Initial value)

MARA is incremented after each data transfer

• If DTSZ = 0, MARA is incremented by 1 after each transfer

• If DTSZ = 1, MARA is incremented by 2 after each transfer

MARA is held fixed

MARA is decremented after each data transfer

• If DTSZ = 0, MARA is decremented by 1 after each transfer

• If DTSZ = 1, MARA is decremented by 2 after each transfer

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