H8SLASH3003 datasheet(240/715 Pages) RENESAS

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8.4.9 Multiple-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1 > channel 2 > channel 3, and

channel A > channel B. Table 8-12 shows the complete priority order. Group 0 and group 1

operate as two independent bus masters.

Table 8-12 Channel Priority Order

Bus Master

Short Address Mode

Full Address Mode

Priority

Group 0

Channel 0A

Channel 0

High

Channel 0B

Channel 1A

Channel 1

Channel 1B

Group 1

Channel 2A

Channel 2

Channel 2B

Channel 3A

Channel 3

Channel 3B

Low

Multiple-Channel Operation in the Same Group: If transfers are requested on two or more

channels simultaneously in the same group, or if a transfer on one channel is requested during a

transfer on another channel in the same group, the DMAC operates as follows.

•

When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it

starts a transfer on the highest-priority channel at that time.

•

Once a transfer starts on one channel, requests to other channels in the same group are held

pending until that channel releases the bus.

•

After each transfer in short address mode, and each externally-requested or cycle-steal

transfer in normal mode, the DMAC releases the bus and returns to step 1. After releasing the

bus, if there is a transfer request for another channel in the same group, the DMAC requests

the bus again.

•

After completion of a burst-mode transfer, or after transfer of one block in block transfer

mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a

higher-priority channel or a bus request from a higher-priority bus master, however, the

DMAC releases the bus after completing the transfer of the current byte or word. After

releasing the bus, if there is a transfer request for another channel in the same group, the

DMAC requests the bus again.

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