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H8/3003 数据表(PDF) 264 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 264 Page - Renesas Technology Corp |
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264 / 715 page ![]() Port 5 Data Direction Register (P5DDR): P5DDR is an 8-bit write-only register that can select input or output for each pin in port 5. Modes 1 and 2 (1-Mbyte Modes): Port 5 functions as a generic input/output port. A pin in port 5 becomes an output pin if the corresponding P5DDR bit is set to 1, and an input pin if this bit is cleared to 0. Modes 3 and 4 (16-Mbyte Modes): All P5DDR bits are fixed at 1 and port 5 functions as part of the address bus. Bits P53DDR to P50DDR are reserved and are also fixed at 1. No bit values can be modified. In modes 1 and 2, P5DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P5DDR is initialized to H'0F by a reset and in hardware standby mode. In software standby mode it retains its previous setting, so if a P5DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Bit Mode 1/2 Initial value Read/Write Initial value Read/Write Mode 3/4 7 P5 DDR 0 W 1 — 7 6 P5 DDR 0 W 1 — 6 5 P5 DDR 0 W 1 — 5 4 P5 DDR 0 W 1 — 4 3 P5 DDR 1 — 1 — 3 2 P5 DDR 1 — 1 — 2 1 P5 DDR 1 — 1 — 1 0 P5 DDR 1 — 1 — 0 Port 5 data direction 7 to 4 These bits select input or output for port 5 pins Reserved bits 246 |
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