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H8/3003 数据表(PDF) 265 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 265 Page - Renesas Technology Corp |
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265 / 715 page ![]() Port 5 Data Register (P5DR): P5DR is an 8-bit readable/writable register that stores data for pins P57 to P54. When a bit in P5DDR is set to 1, if port 5 is read the value of the corresponding P5DR bit is returned directly, regardless of the actual state of the pin. When a bit in P5DDR is cleared to 0, if port 5 is read the corresponding pin level is read. Bits P53 to P50 are reserved. They can be written and read, but they cannot be used for port input or output. P5DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Port 5 Input Pull-Up Control Register (P5PCR): P5PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 5. In modes 1 and 2, when a P5DDR bit is cleared to 0 (selecting generic input), if the corresponding bit from P57PCR to P54PCR is set to 1, the input pull-up transistor is turned on. Bits P53PCR to P50PCR are reserved. They can be written and read, but they do not control input pull-up transistors. P5PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Bit Initial value Read/Write 7 P5 0 R/W 7 6 P5 0 R/W 6 5 P5 0 R/W 5 4 P5 0 R/W 4 3 P5 0 R/W 3 2 P5 0 R/W 2 1 P5 0 R/W 1 0 P5 0 R/W 0 Port 5 data 7 to 4 These bits store data for port 5 pins Reserved bits Bit Initial value Read/Write 7 P5 PCR 0 R/W 7 6 P5 PCR 0 R/W 6 5 P5 PCR 0 R/W 5 4 P5 PCR 0 R/W 4 3 P5 PCR 0 R/W 3 2 P5 PCR 0 R/W 2 1 P5 PCR 0 R/W 1 0 P5 PCR 0 R/W 0 Port 5 input pull-up control 7 to 4 These bits control input pull-up transistors built into port 5 Reserved bits 247 |
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