H8SLASH3003 datasheet(286/715 Pages) RENESAS

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9.9 Port B

9.9.1 Overview

Port B is an 8-bit input/output port that is also used for output (TP15 to TP8) from the

programmable timing pattern controller (TPC), input/output (TIOCB4, TIOCB3, TIOCA4,

TIOCA3) and output (TOCXB4, TOCXA4) by the 16-bit integrated timer-pulse unit (ITU), input

(DREQ1, DREQ0) to the DMA controller (DMAC), and ADTRG input to the A/D converter. Port

B has the same set of pin functions in all operating modes. Figure 9-12 shows the pin

configuration of port B.

Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive a

darlington transistor pair. Pins PB3 to PB0 have Schmitt-trigger inputs.

Figure 9-12 Port B Pin Configuration

9.9.2 Register Descriptions

Table 9-15 summarizes the registers of port B.

Table 9-15 Port B Registers

Address*

Name

Abbreviation

R/W

Initial Value

H'FFD4

Port B data direction register

PBDDR

H'00

H'FFD6

Port B data register

PBDR

R/W

H'00

Note: * Lower 16 bits of the address.

Port B

PB (input/output)/TP

(output)/DREQ (input)/

(input)

PB (input/output)/TP

(output)/DREQ (input)

PB (input/output)/TP

(output)/TOCXB (output)

PB (input/output)/TP

(output)/TOCXA (output)

Port B pins

PB (input/output)/TP

(output)/TIOCB (input/output)

PB (input/output)/TP

(output)/TIOCA (input/output)

PB (input/output)/TP

(output)/TIOCB (input/output)

PB (input/output)/TP

(output)/TIOCA (input/output)

ADTRG

268

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