H8SLASH3003 datasheet(287/715 Pages) RENESAS

287 / 715 page

Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select

input or output for each pin in port B.

A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input

pin if this bit is cleared to 0.

PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.

PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting, so if a PBDDR bit is set to 1, the corresponding pin maintains its

output state in software standby mode.

Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores data for

pins PB7 to PB0.

When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is

returned directly. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin

level is read.

PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Bit

Initial value

Read/Write

PB DDR

Port B data direction 7 to 0

These bits select input or output for port B pins

PB DDR

Bit

Initial value

Read/Write

R/W

Port B data 7 to 0

These bits store data for port B pins

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H8/3003 数据表(PDF) 287 Page - Renesas Technology Corp