AT89C5122D-RDRUM datasheet(150/208 Pages) ATMEL

150 / 208 page

150

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Registers

Timer/Counter Control Register

Reset Value = 0000 0000b

Table 88.

TCON (S:88h)

7654

3210

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit

Number

Bit

Mnemonic

Description

7TF1

Timer 1 Overflow flag

Cleared by the hardware when processor vectors interrupt routine.

Set by the hardware when Timer 1 register overflows.

6TR1

Timer 1 Run Control bit

Clear to turn off Timer/Counter 1.

Set to turn on Timer/Counter 1.

5TF0

Timer 0 Overflow flag

Cleared by the hardware when processor vectors interrupt routine or by software

when the interrupt is disabled

Set by the hardware when Timer 0 register overflows.

4TR0

Timer 0 Run Control bit

Clear to turn off Timer/Counter 0.

Set to turn on Timer/Counter 0.

3IE1

Interrupt 1 Edge flag

Cleared by the hardware when interrupt is processed if edge-triggered (see IT1).

Set by the hardware when external interrupt is detected on the INT1# pin.

2IT1

Interrupt 1 Type Control bit

Clear to select low level active (level triggered) for external interrupt 1 (INT1#).

Set to select falling edge active (edge triggered) for external interrupt 1.

1IE0

Interrupt 0 Edge flag

Cleared by the hardware when interrupt is processed if edge-triggered (see IT0).

Set by the hardware when external interrupt is detected on INT0# pin.

0IT0

Interrupt 0 Type Control bit

Clear to select low level active (level triggered) for external interrupt 0 (INT0#).

Set to select falling edge active (edge triggered) for external interrupt 0.

AT89C5122D-RDRUM 数据表(PDF) 150 Page - ATMEL Corporation

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