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XIO2000AI 数据表(PDF) 97 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI 数据表(HTML) 97 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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97 / 159 page  Classic PCI Configuration Space 87 April 2007 Revised October 2008 SCPS155C 4.67 Clock Mask Register This register selects which PCI bus clocks are disabled when bits 22:20 (POWER_OVRD) in the general control register (offset D4h, see Section 4.65) are set to 010h or 011h. This register has no effect on the clock outputs if the POWER_OVRD bits are not set to 010h or 011h or if the slot power limit is greater than the power required. See Table 4−41 for a complete description of the register contents. PCI register offset: D9h Register type: Read-only, Read/Write Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 4−41. Clock Mask Register Description BIT FIELD NAME ACCESS DESCRIPTION 7 RSVD R Reserved. Returns 0b when read. 6† CLOCK6_MASK RW Clock output 6 mask. This bit disables PCI bus CLKOUT6 when the POWER_OVRD bits are set to 010b or 011b and the slot power limit is exceeded. 0 = Clock enabled (default) 1 = Clock disabled 5† CLOCK5_MASK RW Clock output 5 mask. This bit disables PCI bus CLKOUT5 when the POWER_OVRD bits are set to 010b or 011b and the slot power limit is exceeded. 0 = Clock enabled (default) 1 = Clock disabled 4† CLOCK4_MASK RW Clock output 4 mask. This bit disables PCI bus CLKOUT4 when the POWER_OVRD bits are set to 010b or 011b and the slot power limit is exceeded. 0 = Clock enabled (default) 1 = Clock disabled 3† CLOCK3_MASK RW Clock output 3 mask. This bit disables PCI bus CLKOUT3 when the POWER_OVRD bits are set to 010b or 011b and the slot power limit is exceeded. 0 = Clock enabled (default) 1 = Clock disabled 2† CLOCK2_MASK RW Clock output 2 mask. This bit disables PCI bus CLKOUT2 when the POWER_OVRD bits are set to 010b or 011b and the slot power limit is exceeded. 0 = Clock enabled (default) 1 = Clock disabled 1† CLOCK1_MASK RW Clock output 1 mask. This bit disables PCI bus CLKOUT1 when the POWER_OVRD bits are set to 010b or 011b and the slot power limit is exceeded. 0 = Clock enabled (default) 1 = Clock disabled 0† CLOCK0_MASK RW Clock output 0 mask. This bit disables PCI bus CLKOUT0 when the POWER_OVRD bits are set to 010b or 011b and the slot power limit is exceeded. 0 = Clock enabled (default) 1 = Clock disabled † These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. |
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