XIO2000AI datasheet(54/159 Pages) TAOS

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Feature/Protocol Descriptions

April 2007 Revised October 2008

SCPS155C

Figure 3−18 illustrates a single byte read. The bridge issues a start condition and sends the 7-bit slave device

address and the R/W command bit is equal to 0b (write). The slave device acknowledges if it recognizes the

slave address. Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment

is expected. Then, the bridge issues a restart condition followed by the 7-bit slave address and the R/W

command bit is equal to 1b (read). Once again, the slave device responds with an acknowledge. Next, the

slave device sends the 8-bit data byte, MSB first. Since this is a 1-byte read, the bridge responds with no

acknowledge (logic high) indicating the last data byte. Finally, the bridge issues a stop condition.

Sb6

b3 b2 b1 b0

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Word Address

R/W

Sb6

b3 b2 b1 b0

Slave Address

S/P = Start/Stop Condition

M = Master Acknowledgement

b7 b6

b3 b2 b1 b0

Data Byte

Start

Restart

R/W

A = Slave Acknowledgement

Stop

Figure 3−18. Serial-Bus Protocol—Byte Read

Figure 3−19 illustrates the serial interface protocol during a multi-byte serial EEPROM download. The

serial-bus protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes

are transferred. The number of transferred data bytes is controlled by the bridge master. After each data byte,

the bridge master issues acknowledge (logic low) if more data bytes are requested. The transfer ends after

a bridge master no acknowledge (logic high) followed by a stop condition.

000

Slave Address

Word Address

R/W

Data Byte 1

Data Byte 2

Data Byte 3

M = Master Acknowledgement

S/P = Start/Stop Condition

A = Slave Acknowledgement

Data Byte 0

001

Restart

R/W

Slave Address

Start

Figure 3−19. Serial-Bus Protocol—Multibyte Read

Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the

three previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low). When this control

bit is asserted, the word address and corresponding acknowledge are removed from the serial-bus protocol.

This feature allows the system designer a second serial-bus protocol option when selecting external EEPROM

devices.

3.10.3

Serial-Bus EEPROM Application

The registers and corresponding bits that are loaded through the EEPROM are provided in Table 3−13.

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