XIO2000AI datasheet(67/159 Pages) TAOS

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Classic PCI Configuration Space

April 2007 Revised October 2008

SCPS155C

4.17 Secondary Status Register

The secondary status register provides information about the PCI bus interface. See Table 4−8 for a complete

description of the register contents.

PCI register offset:

1Eh

Read-only, Read/Clear

Default value:

02X0h

BIT NUMBER

RESET STATE

Table 4−8. Secondary Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

PAR_ERR

RCU

Detected parity error. This bit reports the detection of an uncorrectable address, attribute, or data

error by the bridge on its secondary interface. This bit must be set when any of the following three

conditions are true:

• The bridge detects an uncorrectable address or attribute error as a potential target.

• The bridge detects an uncorrectable data error when it is the target of a write transaction.

• The bridge detects an uncorrectable data error when it is the master of a read transaction

(immediate read data).

The bit is set irrespective of the state of bit 0 (PERR_EN) in the bridge control register at offset 3Eh

(see Section 4.29).

0 = Uncorrectable address, attribute, or data error not detected on secondary interface

1 = Uncorrectable address, attribute, or data error detected on secondary interface

SYS_ERR

RCU

Received system error. This bit is set when the bridge detects an SERR assertion.

0 = No error asserted on the PCI interface

1 = SERR asserted on the PCI interface

MABORT

RCU

Received master abort. This bit is set when the PCI interface of the bridge reports the detection of

a master abort termination by the bridge when it is the master of a transaction on its secondary

interface.

0 = Master abort not received on the PCI interface

1 = Master abort received on the PCI interface

TABORT_REC

RCU

Received target abort. This bit is set when the PCI interface of the bridge receives a target abort.

0 = Target abort not received on the PCI interface

1 = Target abort received on the PCI interface

TABORT_SIG

RCU

Signaled target abort. This bit reports the signaling of a target abort termination by the bridge when

it responds as the target of a transaction on its secondary interface.

0 = Target abort not signaled on the PCI interface

1 = Target abort signaled on the PCI interface

10:9

PCI_SPEED

DEVSEL timing. These bits are 01b indicating that this is a medium speed decoding device.

DATAPAR

RCU

Master data parity error. This bit is set if the bridge is the bus master of the transaction on the PCI

bus, bit 0 (PERR_EN) in the bridge control register (offset 3Eh see Section 4.29) is set, and the

bridge either asserts PERR on a read transaction or detects PERR asserted on a write transaction.

0 = No data parity error detected on the PCI interface

1 = Data parity error detected on the PCI interface

FBB_CAP

Fast back-to-back capable. This bit returns a 1b when read indicating that the secondary PCI

interface of bridge supports fast back-to-back transactions.

RSVD

Reserved. Returns 0b when read.

66MHZ

66-MHz capable. The bridge can operate at a maximum CLK frequency of 66 MHz; therefore, this

bit reflects the state of the M66EN terminal.

4:0

RSVD

Reserved. Returns 00000b when read.

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