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数据搜索系统，热门电子元器件搜索 |
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XIO2000AI 数据表(PDF) 71 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI 数据表(HTML) 71 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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71 / 159 page  Classic PCI Configuration Space 61 April 2007 Revised October 2008 SCPS155C 4.27 Interrupt Line Register This read/write register is programmed by the system and indicates to the software which interrupt line the bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet been assigned to the function. Since the bridge does not generate interrupts internally, this register is a scratch pad register. PCI register offset: 3Ch Register type: Read/Write Default value: FFh BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 1 1 1 1 1 1 1 4.28 Interrupt Pin Register The interrupt pin register is read-only 00h indicating that the bridge does not generate internal interrupts. While the bridge does not generate internal interrupts, it does forward interrupts from the secondary interface to the primary interface. PCI register offset: 3Dh Register type: Read-only Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 4.29 Bridge Control Register The bridge control register provides extensions to the command register that are specific to a bridge. See Table 4−17 for a complete description of the register contents. PCI register offset: 3Eh Register type: Read-only, Read/Write, Read/Clear Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4−17. Bridge Control Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:12 RSVD R Reserved. Returns 0h when read. 11 DTSERR RW Discard timer SERR enable. Applies only in conventional PCI mode. This bit enables the bridge to generate either an ERR_NONFATAL (by default) or ERR_FATAL transaction on the primary interface when the secondary discard timer expires and a delayed transaction is discarded from a queue in the bridge. The severity is selectable only if advanced error reporting is supported. 0 = Do not generate ERR_NONFATAL or ERR_FATAL on the primary interface as a result of the expiration of the secondary discard timer. Note that an error message can still be sent if advanced error reporting is supported and bit 10 (DISCARD_TIMER_MASK) in the secondary uncorrectable error mask register (offset 130h, see Section 5.11) is clear (default). 1 = Generate ERR_NONFATAL or ERR_FATAL on the primary interface if the secondary discard timer expires and a delayed transaction is discarded from a queue in the bridge 10 DTSTATUS RCU Discard timer status. This bit indicates if a discard timer expires and a delayed transaction is discarded. 0 = No discard timer error 1 = Discard timer error |
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