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XIO2000AI 数据表(PDF) 81 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI 数据表(HTML) 81 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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81 / 159 page  Classic PCI Configuration Space 71 April 2007 Revised October 2008 SCPS155C 4.49 Device Capabilities Register The device capabilities register indicates the device specific capabilities of the bridge. See Table 4−25 for a complete description of the register contents. PCI register offset: 94h Register type: Read-only Default value: 0000 0D82 BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 Table 4−25. Device Capabilities Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:28 RSVD R Reserved. Returns 0h when read. 27:26 CSPLS RU Captured slot power limit scale. The value in this field is programmed by the host by issuing a Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 9:8 are written to this field. The value in this field specifies the scale used for the slot power limit. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x 25:18 CSPLV RU Captured slot power limit value. The value in this field is programmed by the host by issuing a Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 7:0 are written to this field. The value in this field in combination with the slot power limit scale value (bits 27:26) specifies the upper limit of power supplied to the slot. The power limit is calculated by multiplying the value in this field by the value in the slot power limit scale field. 17:15 RSVD R Reserved. Returns 000b when read. 14 PIP R Power indicator present. This bit is hardwired to 0b indicating that a power indicator is not implemented. 13 AIP R Attention indicator present. This bit is hardwired to 0b indicating that an attention indicator is not implemented. 12 ABP R Attention button present. This bit is hardwired to 0b indicating that an attention button is not implemented. 11:9 EP_L1_LAT RU Endpoint L1 acceptable latency. This field indicates the maximum acceptable latency for a transition from L1 to L0 state. This field can be programmed by writing to the L1_LATENCY field (bits 15:13) in the general control register (offset D4h, see Section 4.65). The default value for this field is 110b which indicates a range from 32 µs to 64 µs. This field cannot be programmed to be less than the latency for the PHY to exit the L1 state. 8:6 EP_L0S_LAT RU Endpoint L0s acceptable latency. This field indicates the maximum acceptable latency for a transition from L0s to L0 state. This field can be programmed by writing to the L0s_LATENCY field (bits 18:16) in the general control register (offset D4h, see Section 4.65). The default value for this field is 110b which indicates a range from 2 µs to 4 µs. This field cannot be programmed to be less than the latency for the PHY to exit the L0s state. 5 ETFS R Extended tag field supported. This field indicates the size of the tag field not supported. 4:3 PFS R Phantom functions supported. This field is read-only 00b indicating that function numbers are not used for phantom functions. 2:0 MPSS R Maximum payload size supported. This field indicates the maximum payload size that the device can support for TLPs. This field is encoded as 010b indicating the maximum payload size for a TLP is 512 bytes. |
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