XIO2000AI datasheet(48/159 Pages) TAOS

48 / 159 page

Feature/Protocol Descriptions

April 2007 Revised October 2008

SCPS155C

In addition, the bridge converts the destination ID device number to one of the AD[31:16] lines as the IDSEL

signal. The implemented IDSEL signal mapping is shown in Table 3−11.

Table 3−11. Type 0 Configuration Transaction IDSEL Mapping

DEVICE

NUMBER

AD[31:16]

00000

0000 0000 0000 0001

00001

0000 0000 0000 0010

00010

0000 0000 0000 0100

00011

0000 0000 0000 1000

00100

0000 0000 0001 0000

00101

0000 0000 0010 0000

00110

0000 0000 0100 0000

00111

0000 0000 1000 0000

01000

0000 0001 0000 0000

01001

0000 0010 0000 0000

01010

0000 0100 0000 0000

01011

0000 1000 0000 0000

01100

0001 0000 0000 0000

01101

0010 0000 0000 0000

01110

0100 0000 0000 0000

01111

1000 0000 0000 0000

1xxxx

0000 0000 0000 0000

Type 1 configuration registers transactions that target a downstream bus other then the secondary bus are

output on the PCI bus as type 1 PCI configuration transactions. Figure 3−7 shows the address phase of a type

1 configuration transaction on the PCI bus as defined by the PCI specification.

Reserved

Bus Number

Device Number

Function

Number

Figure 3−7. Type 1 Configuration Transaction Address Phase Encoding

3.7

PCI Interrupt Conversion to PCI Express Messages

The bridge converts interrupts from the PCI bus sideband interrupt signals to PCI Express interrupt messages.

PCI Express Assert_INTx messages are generated when one of the PCI bus INT[A:D] input terminals

transitions low. The requester ID portion of the Assert_INTx message uses the value stored in the primary bus

number register (see Section 4.11) as the bus number, 0 as the device number, and 0 as the function number.

The tag field for each Assert_INTx message is 00h. The lower two bits in the code field indicate the asserted

interrupt signal.

PCI Express Deassert_INTx messages are generated when one of the PCI bus INT[A:D] input terminals

transitions high. The requester ID portion of the Deassert_INTx message uses the value stored in the primary

bus number register as the bus number, 0 as the device number, and 0 as the function number. The Tag field

for each Deassert_INTx message is 00h. The lower two bits in the code field indicate the deasserted interrupt

signal.

Table 3−12, Figure 3−8, and Figure 3−9 illustrate the format for both the assert and deassert INTx messages.

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