XIO2000AI datasheet(46/159 Pages) TAOS

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Feature/Protocol Descriptions

April 2007 Revised October 2008

SCPS155C

Table 3−10. 32-phase, WRR Arbiter Registers

PCI OFFSET

DESCRIPTION

Classic PCI configuration

General control

(see Section 4.65)

Bit 25 (STRICT_PRIORITY_EN) equal to 0b enables either hardware-fixed,

round-robin or 32-phase, WRR arbitration mode.

PCI Express VC extended

configuration register 15Ch

Port VC control

(see Section 5.19)

Bit 0 (LOAD_VC_TABLE) when written with a 1b transfers the VC arbitration table

configuration register values to the internal registers used by the VC arbiter.

Bits 3:1 (VC_ARB_SELECT) equal to 001b enables 32-phase, WRR arbitration

mode.

PCI Express VC extended

configuration register 15Eh

Port VC status

(see Section 5.20)

Bit 0 (VC_TABLE_STATUS) equal to 1b indicates that the VC arbitration table

configuration registers were updated but not loaded into the internal arbitration

table.

PCI Express VC extended

configuration registers 180h

to 18Ch

VC arbitration table

(see Section 5.27)

4-doubleword sized configuration registers that are the registered version of the

32-phase, WRR VC arbitration table. Each VC arbitration table entry is a 4-bit field.

3.5.4 128-Phase, WRR PCI Port Arbitration Timing

This section includes a timing diagram that illustrates the 128-phase, WRR time-based arbiter timing for the

bridge and three PCI bus devices. This timing diagram assumes aggressive mode since the transfer

associated with device #1 is stopped to start a device #0 transfer. The PCI bus cycle where device #1 is

stopped is indicated by the ‡ symbol. Device #1 then waits until its next port arbitration table cycle to finish

the transfer.

The signal waveforms associated with bridge REQ, bridge GNT, ISOC reference clock, and port arbitration

table entry are internal to the bridge. These internal bridge signals are included here to help clarify the

operation of the PCI port arbiter in 128-phase, WRR time-based arbitration mode. The remaining REQ, GNT,

and PCI bus signals are all external to the bridge.

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