XIO2000AI datasheet(88/159 Pages) TAOS

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Classic PCI Configuration Space

April 2007 Revised October 2008

SCPS155C

4.58 Serial-Bus Control and Status Register

The serial-bus control and status register controls the behavior of the serial-bus interface. This register also

provides status information about the state of the serial bus. See Table 4−32 for a complete description of the

PCI register offset:

B3h

Read-only, Read/Write, Read/Clear

Default value:

00h

BIT NUMBER

RESET STATE

Table 4−32. Serial-Bus Control and Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7†

PROT_SEL

Protocol select. This bit selects the serial-bus address mode used.

0 = Slave address and word address are sent on the serial-bus (default)

1 = Only the slave address is sent on the serial-bus

RSVD

Reserved. Returns 0b when read.

5†

REQBUSY

Requested serial-bus access busy. This bit is set when a software-initiated serial-bus cycle is in

progress.

0 = No serial-bus cycle

1 = Serial-bus cycle in progress

4†

ROMBUSY

Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the bridge is

downloading register defaults from a serial EEPROM.

0 = No EEPROM activity

1 = EEPROM download in progress

3†

SBDETECT

RWU

Serial EEPROM detected. This bit enables the serial-bus interface. The value of this bit controls

whether the GPIO4//SCL and GPIO5//SDA terminals are configured as GPIO signals or as

serial-bus signals. This bit is automatically set to 1b when a serial EEPROM is detected.

Note: A serial EEPROM is only detected once following PERST.

0 = No EEPROM present, EEPROM load process does not happen. GPIO4//SCL and

GPIO5//SDA terminals are configured as GPIO signals.

1 = EEPROM present, EEPROM load process takes place. GPIO4//SCL and GPIO5//SDA

terminals are configured as serial-bus signals.

2†

SBTEST

Serial-bus test. This bit is used for internal test purposes. This bit controls the clock source for the

serial interface clock.

0 = Serial-bus clock at normal operating frequency ~ 60 kHz (default)

1 = Serial-bus clock frequency increased for test purposes ~ 4 MHz

1†

SB_ERR

RCU

Serial-bus error. This bit is set when an error occurs during a software-initiated serial-bus cycle.

0 = No error

1 = Serial-bus error

0†

ROM_ERR

RCU

Serial EEPROM load error. This bit is set when an error occurs while downloading registers from a

serial EEPROM.

0 = No error

1 = EEPROM load error

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

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